One of the novelties that Pat Gelsinger’s have integrated into their processors from the current Rocket Lake-S They are called Gear Modes. Where in the first one the memory controller clock speed is 1 to 1, while in the second it is reduced by half. The consequences of it? RAM support with higher bandwidth, but in exchange for more access latency.

This novelty has also been integrated into Alder Lake-S, where it inherits the BMI of its predecessor, with the difference that it has been adapted to DDR5 and adds Gear 4 mode, which reduces to a quarter the speed of the bus between the CPU and the RAM. Of course, this has consequences on processor performance, but what about memory?

Alder Lake-S Gear 4 brings great latency

A new benchmark related to the Intel Gen 12 for desktop has appeared, in this case we are talking about a CPU with Alder Lake-S architecture, specifically the Core i5-12600K, composed of a 10-core configuration in P configuration. -Cores and E-Cores of 6 + 4.

The performance test has been done using the AIDA64 Caché & Memory test on a PC with DDR5-6400 and the processor in Gear 4 mode. The results? Despite the impressive 88-90 gigabytes per second of bandwidth, latency goes up to 92.5 ns. The last figure is very high, since this means that the new memory controller mode increases the response time of the CPU with the RAM to almost double it in order to support the high speeds of DDR5, which would break the advantage of this type of memory compared to DDR4.

Render Intel Alder Lake

It must be taken into account that in a CPU latency is much more important than bandwidth, since this is more sensitive when executing the instructions of the communication time with the RAM than the data that is transmitted. In any case, it must be clarified that officially the maximum supported by Alder Lake-S CPUs would be DDR5-4800 (without overclock) and faster memory types are not recommended by Intel due to the lower performance given their higher latency.

The use of a Northbridge as an IMC integrated in the CPU is not new, but it has been in recent years, since they depend on the communication clock speed with the memory controller. Being the Zen architecture in all its generations the first that brought this change in the PC processors.